Characterization and Design Consideration of 80-nm Self-Aligned N-/P-Channel I-MOS Devices

80-nm self-aligned nand p-channel I-MOS devices were demonstrated by using a novel fabrication method featuring double sidewall spacer, elevated drain structure and RTA process. The fabricated devices showed a normal transistor operation with extremely small subthreshold swing less than 12.2 mV/dec at room temperature. The nand p-channel I-MOS devices had an ON/OFF current of 394.1/0.3 μA and 355.4/8.9 μA per μm, respectively. We also investigated some critical issues in device design such as the junction depth of the source extension region and the substrate doping concentration.